Technical Program

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Advanced Program Layout
Day 1 : July 25
08:30 - 17:00 Registration
09:00 - 09:10 Opening
09:10 - 10:10 Invited Keynote Lecture 1 (Chair: Hayden So)
 

Is Anybody Out There? Signal Processing Instrumentation for SETI

Dan Werthimer
Chief Scientist, SETI@home and Berkeley SETI research center, USA

10:10 - 10:40 Coffee Break
10:40 - 12:00 Session 1 : Architecture & system I (Chair: Yuichiro Shibata)
 

Application-Aware Collective Communication on FPGA Clusters

Jiayi Sheng, Qingqing Xiong, Chen Yang and Martin Herbordt

Cost-Effective and High-Throughput Merge Network Architecture for the Fastest FPGA Sorting Accelerator

Susumu Mashimo, Thiem Van Chu and Kenji Kise

FPGA-based Multicore Architecture for Integrating Multiple DDoS Defense Mechanisms

Cuong Pham-Quoc, Biet Nguyen and Tran Ngoc Thinh

Performance Evaluation of PEACH3:
Field Programmable Gate Array Switch for Tightly Coupled Accelerators

Takahiro Kaneda, Chiharu Tsuruta, Toshihiro Hanawa and Hideharu Amano

12:00 - 14:00 Lunch
14:00 - 14:55 Session 2 : Design methodology & tool I (Chair: Diana Goehringer)
 

An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug

Fatemeh Eslami and Steven Wilton

A High-speed Verilog HDL Simulation Method using a Lightweight Translator

Ryohei Kobayashi, Tomohiro Misono and Kenji Kise

An HLS Framework for Building-Cube Based Streamed Stencil Computation on FPGA Accelerators

Rie Soejima, Ryo Fujita, Yuichiro Shibata and Kiyoshi Oguri

14:55 - 15:30 PhD Forum (Chair: Wei ZHANG)
15:30 - 16:30 Poster Session I (Chair: Wei ZHANG)
17:00 - 18:30 Design Competition (Chair: Sham, Bruce)
18:00 - 20:00 Welcome Reception


Day 2 : July 26
08:40 - 16:00 Registration
09:00 - 10:00 Invited Keynote Lecture 2 (Chair: Wayne Luk)
 

Accelerating Hyperscale Datacenter Services with FPGAs -- Microsoft Catapult

Andrew Putnam
Principal Research Hardware Development Engineer, Microsoft Research, USA

10:00 - 10:30 Coffee Break
10:30 - 11:50 Session 3 : Application I (Chair: Martin Herbordt)
 

An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search

Shohei Sassa, Kenji Kanazawa, Shaowei Cai and Moritoshi Yasunaga

An Efficient GPU-Accelerated Implementation of Genomic Short Read Mapping with BWA-MEM

Ernst Houtgast, Vlad-Mihai Sima, Koen Bertels and Zaid Al-Ars

An FFT circuit based on Nested RNS using Constant Division Algorithm

Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi and Kazumasa Iwai

Performance Evaluation of Inter-Cube Data Exchange
in FPGA-based Fluid Simulation with Building Cube Method

Daichi Tanaka, Tomoya Ueno, Kentaro Sano and Satoru Yamamoto

11:50 - 14:00 Lunch
14:00 - 15:20 Session 4 : Architecture & system II (Chair: Kenji Kise)
 

Novel Three-Dimensional Embedded FPGA Technology And Architectures

Vinod Pangracious and Mulhim Al-Doori

Migration of long-running Tasks between Reconfigurable Resources using Virtualization

Oliver Knodel, Paul R. Gen├čler and Rainer G. Spallek

Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units

Jubee Tada, Maiki Hosokawa, Ryusuke Egawa and Hiroaki Kobayashi

Accelerating Spark Framework Using Local and Remote GPU Devices

Yasuhiro Ohno, Shin Morishima and Hiroki Matsutani

15:20 - 16:20 Poster Session II (Chair: Ray Cheung)
16:20 - 17:20 Invited Talk -

"Software Defined, Hardware Optimization - Tools in Xilinx All Programmable Technology"

Min Ma, Senior Engineer, Xilinx

17:30 Coach bus depart for Banquet
18:00 - 21:00 Banquet



Day 3 : July 27
08:40 - 12:00 Registration
09:00 - 10:20 Session 5 : Application II (Chair: Kentaro Sano)
 

Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms

Jiang Su, Jiangxiong Liu, David B. Thomas and Peter Y. K. Cheung

High-level synthesis design optimization for blocked floating-point matrix multiplication

Erik D'Hollander

FPGA-based Volleyball Player Tracker

Chengzhe Li, Hiroshi Maruyama and Yoshiki Yamaguchi

Position Representation and Game Play Architecture for Trax on an FPGA

Donald G. Bailey

10:20 - 10:50 Coffee Break
10:50 - 11:45 Session 6 : Design methodology & tool II (Chair: Michael Huebner)
 

A Study of Heterogeneous Computing Design Method based on Virtualization Technology

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi

FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels

Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So and Haigang Yang

Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design (Short)

Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S K Nandy and Ranjani Narayan

11:45 - 12:00 Closing and Announcement of HEART2017
12:00 - 14:00 Lunch

 

Poster Sessions

Day-1 Posters: Poster Session I and PhD Forum
 

Performance Evaluation of PEACH3:
Field Programmable Gate Array Switch for Tightly Coupled Accelerators

Takahiro Kaneda, Chiharu Tsuruta, Toshihiro Hanawa and Hideharu Amano

An HLS Framework for Building-Cube Based
Streamed Stencil Computation on FPGA Accelerators

Rie Soejima, Ryo Fujita, Yuichiro Shibata and Kiyoshi Oguri

Breadth-first Search on Suiren: a compact supercomputer

Takuji Mitsuishi, Takahiro Kaneda, Hideharu Amano and Sunao Torii

Towards low-latency data exchange with fine-grained accelerators on programmable SoCs [PhD Forum]

Alexander Kroh

In-situ Object Detection and Classification on FPGA for Asymmetric-Detection Time-Stretch Optical Microscopy [PhD Forum]

Maolin Wang

Novel Coarse Grained Re-configurable Array (CGRA) to reduce hardware compilation time [PhD Forum]

Ponni Mohanakumari

Vertex-centric Distributed Graph Processing on FPGA [PhD Forum]

Nina Engelhardt

Customizable Generation and Optimization of Monte Carlo Architectures [PhD Forum]

Ben Lindsey

Day-2 Posters: Poster Session II
 

Accelerating Spark Framework Using Local and Remote GPU Devices

Yasuhiro Ohno, Shin Morishima and Hiroki Matsutani

Performance Evaluation of Inter-Cube Data Exchange
in FPGA-based Fluid Simulation with Building Cube Method

Daichi Tanaka, Tomoya Ueno, Kentaro Sano and Satoru Yamamoto

Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design

Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S K Nandy and Ranjani Narayan

A survey of PCIe Gen3, 100GbE and 200GbE on FPGAs

Hirotaka Takayama, Yoshiki Yamaguchi and Taisuke Boku

FDeX: Memory Expansion Method with Skewed DRAM Cache and FPGA BlockRAMs

Shingo Ohya, Eri Ogawa and Kenji Kise

Efficiently Exploiting On-Chip RAMs of FPGA to Accelerate In-Memory Hash Joins

Behzad Salami, Oriol Arcas-Abella, Nehir Sonmez, Osman Unsal and Adrian Cristal

Position Representation and Game Play Architecture for Trax on an FPGA

Donald G. Bailey

 

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